In the manufacturing of integrated circuits (ICs), measuring the overlay of the patterning of a second level on a semiconductor wafer relative to the patterning of a first level is achieved by analysis of the optical image of an assembly or arrangement of features referred to as a "target." Such feature assemblies are fabricated on the wafer surface at the same die site using the same processes and tools used to form the working features of the integrated circuit itself. The purpose of this approach is to provide an overlay metrology as a means for monitoring the quality of the fabrication process. As discussed below, problems are created when the optical image of the target is severely obstructed by new fabrication techniques now being introduced by IC manufacturers.
Referring to FIG. 1, one of several standard target architectures is shown. The illustrated target architecture is the conventional "bars-in-bars" configuration and comprises two orthogonal sets of spaced, parallel inner bars 10 patterned in the same conductor material of the first level and two further sets orthogonal of spaced, parallel outer bars 12 patterned in the material of the second level. One of the sets of the bars 10 and 12 usually comprises photoresist material. Optical instruments (not shown) are used to provide on-wafer overlay metrology whereby to extract the overlay vector. This is represented schematically in FIG. 2 wherein the bars 10' and 12' of the bars-in-bars pattern are out of registration and the corresponding overlay vector is indicated at 14.
In interconnect fabrication, i.e., wafer fabrication wherein there is an interconnection between levels, there are two key and distinct metrology-overlay applications in which the second level is patterned in resist, i.e., using a photoresist material. In "Type A" applications illustrated in FIG. 3, the overlay of patterned resist 12 (the second level), which is deposited over or on a dielectric film 14, is measured relative to conducting elements or features 10 buried by, i.e., disposed within, the dielectric film 14, as illustrated. Typically, the resist patterning at a die site determines where "vias," i.e., transverse (vertical) connection passages between levels, are etched through the dielectric film 14 to facilitate the formation of electrical interconnections referred as "plugs" (not shown). These plugs usually are made of the refractory metal tungsten. Because the dielectric film is usually optically transparent, light scattered from the buried elements or features 10 effectively contributes to the referenced optical image from which the overlay vector described above can be extracted by pattern recognition-analysis techniques.
In "Type B" applications, illustrated in FIG. 4, the patterned resist 12 is deposited over an optically opaque film 16 made of conducting material, usually aluminum. This resist patterning determines the overlay of subsequent patterning of the overlying film 16 of conducting material relative to previously formed tungsten interconnection plugs 18 providing electrical connection to the lower surface of film 16. The value of the overlay vector between the interconnection plugs 18 and the resist patterning 12 is a critical manufacturing specification and is the subject of the metrology. However, because the tungsten interconnection plugs 18 are optically concealed, the plugs 18 cannot contribute directly to build the optical image of the target without additional processing aimed at revealing the buried plug location. Recent practice has been to extract the overlay vector from an image contribution rendered by residual topographical features, indicated at 19 in FIG. 4, that are propagated to the upper surface of the opaque film 16 by the wafer-processing dynamics.
In modern IC fabrication, the preferred technology for synthesizing multi-level interconnect systems uses CMP (Chemical-Mechanical Polishing) planarization to facilitate high resolution lithography through the minimization of adverse depth-of-focus limitations or effects. In principle, overlay metrology in Type A applications (wherein, as shown in FIG. 3, a transparent layer 14 separates the patterned levels 10 and 12 the overlapping of which is being examined) is not adversely affected by the use of CMP planarization processes. However, in type B applications, optical metrology is ineffective when, referring to FIG. 4, the upper surface of the opaque film 16 is rendered topographically featureless by the practice of CMP. In other words, the shallow residual topographical features 19 are essentially erased or smoothed out when CMP is used, and thus no residual features are left to be employed to extract the overlay vector. The prior art does not provide a method or means for locating the concealed tungsten features 18 so as to enable overlay metrology in Type B applications wherein CMP is employed.